1Features
- Reads absolute encoders over SSI (synchronous serial interface)
- Acts as the master: drives the clock and shifts in the position word
- SPI-like serial read over just a clock and a data line
- Written in VHDL and packaged as a reusable Vivado IP block
2Specifications
- Interface
- SSI
- Behaviour
- SPI-like master
- Language
- VHDL
- Toolchain
- Vivado
3Figure 1 — Board
4On the bench
5Description
Many absolute encoders report their position over SSI: the reader drives a clock, and the encoder shifts its position word out one bit per edge. In practice it behaves a lot like an SPI read, over just a clock and a data line.
I wrote the reader in VHDL and packaged it as a Vivado IP block, so an FPGA design can drop it in and get the encoder position without re-implementing the protocol each time.
6Design tools
VivadoVHDL